The present invention relates generally to a conductor structure for a magnetic memory device. More specifically, the present invention relates to a conductor structure for a magnetic memory device in which a cross-sectional area of a conductor is decreased to increase a current density in the conductor or in which the cross-sectional area is increased to reduce a resistance to a flow of electrons in the conductor and the conductor is partially cladded to increase a magnetic field such that a reduced amount of current is required to write a bit of data to the magnetic memory device.
Magnetic Random Access Memory (MRAM) is an emerging technology that can provide an alternative to traditional data storage technologies. MRAM has desirable properties including fast access times like DRAM and non-volatile data retention like hard disc drives. MRAM stores a bit of data (i.e. information) as an alterable orientation of magnetization in a patterned thin film magnetic element that is referred to as a data layer, a storage layer, or a data film. The data layer is designed so that it has two stable and distinct magnetic states that define a binary one (xe2x80x9c1xe2x80x9d) and a binary zero (xe2x80x9c0xe2x80x9d). Although the bit of data is stored in the data layer, many layers of carefully controlled magnetic and dielectric thin film materials are required to form a complete magnetic memory element. One prominent form of magnetic memory element is a spin tunneling device. The physics of spin tunneling is complex and good literature exits on this subject.
In FIG. 1a, a prior MRAM memory element 101 includes a data layer 102 and a reference layer 104 that are separated by a thin barrier layer 106. Typically the barrier layer 106 has a thickness that is less than about 2.0 nm. The memory element 101 has a width W and a height H and a ratio of the width W to the height H defines an aspect ratio (i.e. aspect ratio=W÷H). In a tunneling magnetoresistance (TMR) structure the barrier layer 106 is an electrically non-conductive dielectric material such as aluminum oxide (Al2O3), for example. Whereas, in a giant magnetoresistance (GMR) structure the barrier layer 106 is a thin layer of conductive material such as copper (Cu), for example. The reference layer 104 has a pinned orientation of magnetization 108, that is, the pinned orientation of magnetization 108 is fixed in a predetermined direction and does not rotate in response to an external magnetic field. In contrast the data layer 102 has an alterable orientation of magnetization 103 that can rotate between two orientations in response to an external magnetic field.
In FIG. 1b, when the pinned orientation of magnetization 108 and the alterable orientation of magnetization 103 point in the same direction (i.e. they are parallel to each other) the data layer 102 stores a binary one (xe2x80x9c1xe2x80x9d). On the other hand, when the pinned orientation of magnetization 108 and the alterable orientation of magnetization 103 point in opposite directions (i.e. they are anti-parallel to each other) the data layer 102 stores a binary zero (xe2x80x9c0xe2x80x9d).
In FIG. 2, the prior memory element 101 is typically positioned at an intersection of two orthogonal conductors 105 and 107. For instance, the conductor 105 can be a word line and the conductor 107 can be a bit line. A bit of data is written to the memory element 101 by generating two magnetic fields HX and HY that are in turn generated by currents IY and IX flowing in the conductors 107 and 105 respectively. The magnetic fields HX and HY cooperatively interact with the data layer 102 to rotate the alterable orientation of magnetization 103 from its current orientation to a new orientation. Therefore, if the current orientation is parallel (i.e. positive x-direction on the x axis) with the pinned orientation of magnetization 108 such that a binary xe2x80x9c1xe2x80x9d is stored in the data layer 102, then the magnetic fields HX and HY will rotate the alterable orientation of magnetization 103 to an anti-parallel orientation (i.e. negative x-direction on the x axis) such that a binary xe2x80x9c0xe2x80x9d is stored in the data layer 102.
In FIG. 3, the prior memory element 101 is positioned in a large array 201 of similar memory elements 101 that are also positioned at an intersection of a plurality of the conductors 107 and 105 that are arranged in rows and columns. For purposes of illustration, in FIG. 3, the conductors 107 are bit lines and the conductors 105 are word lines. The conductors (105, 107) need not be in direct contact with the memory element 101. Typically, one or more layers of material separate the conductors (105, 107) from the data layer 102 and the reference layer 104.
A bit of data is written to a selected one of the memory elements 101 that is positioned at an intersection of a word and bit line by passing the currents IY and IX through the word and bit lines. During a normal write operation the selected memory element 101 will be written to only if the combined magnetic fields HX and HY are of a sufficient magnitude to switch (i.e. rotate) the alterable orientation of magnetization of the memory element 101.
One disadvantage of the prior memory element 101 is that the conductors 107 and 105 have a nominal thickness denoted as tN and a width WB and WW respectively that are substantially equal to the width W and height H of the memory element 101. In FIG. 4, a cross-sectional view of the memory element 101 along the y-axis Y illustrates the conductor 107 as having a width WB that is substantially equal to the width W of the memory element 101. Similarly, a cross-sectional view of the memory element 101 along the x-axis X illustrates the conductor 105 as having a width WW that is substantially equal to the height H of the memory element 101.
As a result of the above mentioned thicknesses tN and widths (WB and WW), the magnitude of the currents IY and IX required to generate the combined magnetic fields HX and HY is high. There are several disadvantages to high currents. First, the transistor driver circuits for sourcing those currents are sized based on the amount of current required. Consequently, higher currents require larger driver circuits. As the dimensions of the memory elements 101 shrink to increase areal density, it is desirable to also shrink the size of the driver circuits so that the amount of area occupied by the array 201 is minimized.
Second, in portable electronics applications where the power source is typically a battery, high current demands result in a reduction in battery life and can require larger and heavier batteries. It is desirable to reduce weight, size, and to increase battery life for longer operating times.
Finally, in low power applications, the waste heat generated by a microelectronic device is proportional to the amount of current supplied. Therefore, waste heat generation increases with higher current demands. Excessive waste heat generation can elevate the temperature of the device, often with deleterious effects.
U.S. Pat. No. 6,236,590 to Bhattacharyya et al., discloses a conductor layout structure in which the amount of current required to switch the data layer is reduced by reducing the width of the conductors such that the edges of the conductors are within the width or the length of the memory element in the direction the conductor crosses the memory element. However, further reductions in current are required as the dimensions of magnetic memory elements continue to shrink. Therefore, there is room for further reductions in current consumption during write operations in MRAM devices.
Consequently, there exists a need for a conductor structure for a magnetic memory cell that provides optimal use of current to switch the data layer of the memory cell. There is also a need for a conductor structure for a magnetic memory cell that uses the available current more efficiently than the prior conductor structures. There exists a need for a conductor structure for a magnetic memory cell that reduces the need for high current driver circuits. Finally, there is a need for a conductor structure for a magnetic memory cell that further reduces current consumption during write operations to the memory cell.
The present invention address the above mentioned needs by using a conductor structure in which a width and a thickness of the conductor is reduced to increase a current density in the conductor so that a magnitude of a magnetic field sufficient to switch an alterable orientation of magnetization of a data layer of a memory cell can be generated by a reduced magnitude of current flowing in the conductor. Essentially, as the conductor width and thicknesses are decreased, a switching current requirement also decreases. The reduction in conductor width and thickness can be relative to a nominal width and a nominal thickness. Furthermore, the reduction in conductor width and thickness can be on one or more conductors that are operative to write data to the data layer of the memory cell.
In an alternative embodiment of the present invention, a width of the conductor is reduced and a thickness of the conductor is increased so that a resistance to the flow of a current in the conductor is reduced. The conductor is partially cladded with a soft magnetic material so that the magnetic field is increased and a magnitude of a magnetic field sufficient to switch an alterable orientation of magnetization of the data layer of the memory cell can be generated by a reduced magnitude of current flowing in the conductor. The reduction in conductor width and the increase in conductor thickness can be relative to a nominal width and a nominal thickness. The decrease in conductor width and the increase in conductor thickness can be on one more conductors that are operative to write data to the data layer of the memory cell.
In another embodiment of the present invention, the conductors are split into two or more spaced apart segments. The spaced apart segment can also be partially cladded.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.